3.15.5 Substrate Parasitics

In multi-gate devices such as the FinFET, there is capacitive coupling from the source/drain to the substrate through the buried oxide. This component is modeled in BSIM-CMG and is given by:

$C_{sbox} = C_{box} \cdot ASEO + C_{box,sw} \cdot (PSEO - FPITCH \cdot NFIN_{total}) \qquad (3.482)$

$C_{dbox} = C_{box} \cdot ADEO + C_{box,sw} \cdot (PDEO - FPITCH \cdot NFIN_{total}) \qquad (3.483)$

where the side component per width is [13]

$C_{box,sw} = CSDESW \cdot ln \Big( 1 + \dfrac{HFIN}{EOTBOX} \Big) \qquad (3.484)$

There is also direct capacitive coupling from the gate to the substrate in FinFETs (Fig. 6). Following BSIM4 [10] this component is given by

$C_{ge,overlap} = (CGBO \cdot NF \cdot NGCON + CGBN \cdot NFIN_{total}) \cdot (L + XL) \qquad (3.485)$

$C_{sbox}$, $C_{dbox}$ and $C_{ge,overlap}$ are all linear capacitors.

Figure 6: Illustration of the direct gate to substrate overlap region in the FinFET.

References

[10] BSIM4 model. Department of Electrical Engineering and Computer Science, UC Berkeley.

[13] BSIM-SOI model. Department of Electrical Engineering and Computer Science, UC Berkeley.