3.15 Parasitic Resistances and Capacitance Models

In this section we will describe the models for parasitic resistances and capacitances in BSIM-CMG.

BSIM-CMG models the parasitic source/drain resistance in two components: a bias dependent extension resistance and a bias independent diffusion resistance. Parasitic gate resistance is modeled as well.

The parasitic capacitance model in BSIM-CMG includes a bias-indepedent fringe capacitance, a bias-dependent overlap capacitance, and substrate capacitances. In the case of MuGFETs on SOI, the substrate capacitances are from source/drain/gate to the substrate through the buried oxide. For MuGFETs on bulk substrate, an additional junction capacitor is modeled, which we will describe along with the junction current model in Section 3.20.