3.2 Terminal Voltages

Terminal voltages and $V_{dsx}$ calculations:

$devsign = \begin{cases} 1 &\text{for NMOS} \\ -1 &\text{for PMOS} \end{cases} \qquad (3.207)$

$V_{gs\_noswap} = devsign \cdot \Big[ V(`IntrinsicGate) - V(si) \Big] \qquad (3.208)$

$V_{ds\_noswap} = devsign \cdot \Big[ V(di) - V(si) \Big] \qquad (3.209)$

$V_{gd\_noswap} = devsign \cdot \Big[ V(`IntrinsicGate) - V(di) \Big] \qquad (3.210)$

$V_{es\_jct} = devsign \cdot \Big[ V(e) - V(si) \Big] \qquad (3.211)$

$V_{ed\_jct} = devsign \cdot \Big[ V(e) - V(di) \Big] \qquad (3.212)$

$V_{ge} = V(`IntrinsicGate) - V(e) \qquad (3.213)$

$sigvds = 1.0 \qquad (3.214)$

If $V_{ds\_noswap} < 0.0$ then,

$sigvds = -1.0 \qquad (3.215)$

$V_{gs} = V_{gs\_noswap} - V_{ds\_noswap} \qquad (3.216)$

$V_{ds} = -1.0 \cdot V_{ds\_noswap} \qquad (3.217)$

$V_{es} = V_{ed\_jct} \qquad (3.218)$

else

$V_{gs} = V_{gs\_noswap} \qquad (3.219)$

$V_{ds} = V_{ds\_noswap} \qquad (3.220)$

$V_{es} = V_{es\_jct} \qquad (3.221)$

$V_{dsx} = \sqrt{V_{ds}^2 + 0.01} - 0.1 \qquad (3.222)$

In $RDSMOD = 1$ a resistor is added to the intrinsic FET element topology between the intrinsic source and the extrinsic source and a resistor is added to the intrinsic FET element topology between the intrinsic drain and the extrinsic drain. The external source/drain nodes are still labeled $s$ and $d$ while the intrinsic source and intrinsic drain nodes are labeled $si$ and $di$ respectively.

$V(si, s) = V_{si} - V_s \qquad (3.223)$

$V(di, s) = V_{di} - V_d \qquad (3.224)$